| Pass-transistor adiabatic logic with NMOS pull-down configuration F Liu, KT Lau Electronics Letters 34 (8), 739-741, 1998 | 103 | 1998 |
| Designing CMOS folded-cascode operational amplifier with flicker noise minimisation PK Chan, LS Ng, L Siek, KT Lau Microelectronics Journal 32 (1), 69-73, 2001 | 46 | 2001 |
| Improved adiabatic pseudo-domino logic family KT Lau, F Liu Electronics Letters 33 (25), 2113-2114, 1997 | 32 | 1997 |
| Low cost RF identification and locating system TH Ooi, CH Lim, KT Lau IEEE transactions on consumer electronics 35 (4), 831-839, 1989 | 31 | 1989 |
| Adiabatic pseudo-domino logic WY Wang, KT Lau Electronics letters 31 (23), 1982-1983, 1995 | 27 | 1995 |
| Low power flip-flop design based on PAL-2N structure KW Ng, KT Lau Microelectronics Journal 31 (2), 113-116, 2000 | 26 | 2000 |
| Approximate adder for low-power computations I Alam, KT Lau International Journal of Electronics Letters 5 (2), 158-165, 2017 | 23 | 2017 |
| A novel adiabatic register file design KW Ng, KT Lau Journal of Circuits, Systems, and Computers 10 (01n02), 67-76, 2000 | 19 | 2000 |
| Improved structure for efficient charge recovery logic F Liu, KT Lau Electronics Letters 34 (18), 1731-1732, 1998 | 19 | 1998 |
| Four-quadrant CMOS analogue multiplier for artificial neural networks ST Lee, KT Lau, L Siek Electronics Letters 31 (1), 48-49, 1995 | 19 | 1995 |
| Transmission gate-interfaced APDL design KT Lau, WY Wang Electronics Letters 32 (4), 317-318, 1996 | 18 | 1996 |
| ECRL-based low power flip-flop design KW Ng, KT Lau Microelectronics journal 31 (5), 365-370, 2000 | 15 | 2000 |
| Four-phase improved adiabatic pseudo-domino logic KT Lau, F Liu Electronics Letters 34 (4), 343-344, 1998 | 13 | 1998 |
| A microprocessor-based gate security system KT Lau, YK Choo IEEE transactions on consumer electronics 35 (4), 858-862, 1989 | 12 | 1989 |
| Low power 16× 16 bit multiplier design using PAL-2N logic family HH Wong, KT Lau Journal of Circuits, Systems, and Computers 11 (02), 155-163, 2002 | 11 | 2002 |
| Low power building block for artificial neural networks ST Lee, KT Lau Electronics Letters 31 (19), 1618-1619, 1995 | 11 | 1995 |
| Improved PAL-2N logic with complementary pass-transistor logic evaluation tree KW Ng, KT Lau Microelectronics journal 31 (1), 55-59, 2000 | 10 | 2000 |
| Four-quadrant analogue CMOS multiplier cell for VLSI signal and information processing KT Lau, ST Lee, VKS Ong IEE Proceedings-Circuits, Devices and Systems 145 (2), 132-134, 1998 | 10 | 1998 |
| A PC-based MPEG compressed data decoder TH Ooi, KT Lau, CM Lim, KS Yeo, YE Yip, KA Pok, CJ Wong IEEE transactions on consumer electronics 41 (4), 1169-1173, 1995 | 10 | 1995 |
| Smart card reader CH Lim, YH Dan, KT Lau, KY Choo IEEE transactions on consumer electronics 39 (1), 6-12, 1993 | 10 | 1993 |
Liter SiekAssociate Professor, Nanyang Technological UniversityVerified email at ntu.edu.sg
