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Matthew Mattina
Matthew Mattina
Affiliazione sconosciuta
Email verificata su alumni.princeton.edu
Titolo
Citata da
Citata da
Anno
On-chip interconnection architecture of the tile processor
D Wentzlaff, P Griffin, H Hoffmann, L Bao, B Edwards, C Ramey, ...
IEEE micro 27 (5), 15-31, 2007
12362007
Tile64-processor: A 64-core soc with mesh interconnect
S Bell, B Edwards, J Amann, R Conlin, K Joyce, V Leung, J MacKay, ...
2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008
8562008
Federated learning based on dynamic regularization
DAE Acar, Y Zhao, RM Navarro, M Mattina, PN Whatmough, V Saligrama
arXiv preprint arXiv:2111.04263, 2021
7802021
Computing in parallel processing environments
PR Griffin, M Hostetter, A Agarwal, CC Miao, CD Metcalf, B Edwards, ...
US Patent 8,738,860, 2014
4072014
Scale-sim: Systolic cnn accelerator simulator
A Samajdar, Y Zhu, P Whatmough, M Mattina, T Krishna
arXiv preprint arXiv:1811.02883, 2018
3082018
Micronets: Neural network architectures for deploying tinyml applications on commodity microcontrollers
C Banbury, C Zhou, I Fedorov, R Matas, U Thakker, D Gope, ...
Proceedings of machine learning and systems 3, 517-532, 2021
2592021
A systematic methodology for characterizing scalability of dnn accelerators using scale-sim
A Samajdar, JM Joseph, Y Zhu, P Whatmough, M Mattina, T Krishna
2020 IEEE International Symposium on Performance Analysis of Systems and …, 2020
1862020
Sparse: Sparse architecture search for cnns on resource-constrained microcontrollers
I Fedorov, RP Adams, M Mattina, P Whatmough
Advances in Neural Information Processing Systems 32, 2019
1862019
Last level cache (llc) performance of data mining workloads on a cmp-a case study of parallel bioinformatics workloads
A Jaleel, M Mattina, B Jacob
The Twelfth International Symposium on High-Performance Computer …, 2006
1792006
Tarantula: a vector extension to the alpha architecture
R Espasa, F Ardanaz, J Emer, S Felix, J Gago, R Gramunt, I Hernandez, ...
ACM SIGARCH Computer Architecture News 30 (2), 281-292, 2002
1512002
High performance, scalable multi chip interconnect
CG Ramey, M Mattina
US Patent 9,424,228, 2016
1312016
Caching in multicore and multiprocessor architectures
A Agarwal, IR Bratt, M Mattina
US Patent 7,805,575, 2010
1142010
Euphrates: Algorithm-soc co-design for low-power mobile continuous vision
Y Zhu, A Samajdar, M Mattina, P Whatmough
arXiv preprint arXiv:1803.11232, 2018
1112018
TinyLSTMs: Efficient neural speech enhancement for hearing aids
I Fedorov, M Stamenovic, C Jensen, LC Yang, A Mandell, Y Gan, ...
arXiv preprint arXiv:2005.11138, 2020
1042020
Scale-sim: Systolic CNN accelerator
A Samajdar, Y Zhu, PN Whatmough, M Mattina, T Krishna
arXiv preprint arXiv:1811.02883 57, 2018
882018
Managing cache memory in a parallel processing environment
D Wentzlaff, M Mattina, A Agarwal
US Patent 7,882,307, 2011
862011
Systolic tensor array: An efficient structured-sparse GEMM accelerator for mobile CNN inference
ZG Liu, PN Whatmough, M Mattina
IEEE Computer Architecture Letters 19 (1), 34-37, 2020
802020
S2ta: Exploiting structured sparsity for energy-efficient mobile cnn acceleration
ZG Liu, PN Whatmough, Y Zhu, M Mattina
2022 IEEE International Symposium on High-Performance Computer Architecture …, 2022
742022
Debiasing model updates for improving personalized federated training
DAE Acar, Y Zhao, R Zhu, R Matas, M Mattina, P Whatmough, ...
International conference on machine learning, 21-31, 2021
702021
Mapping memory in a parallel processing environment
D Wentzlaff, M Mattina, A Agarwal
US Patent 7,620,791, 2009
642009
Il sistema al momento non può eseguire l'operazione. Riprova più tardi.
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