| Impact of precisely positioned dopants on the performance of an ultimate silicon nanowire transistor: A full three-dimensional NEGF simulation study VP Georgiev, EA Towie, A Asenov IEEE Transactions on Electron Devices 60 (3), 965-971, 2013 | 29 | 2013 |
| Simulation study of the impact of quantum confinement on the electrostatically driven performance of n-type nanowire transistors Y Wang, T Al-Ameri, X Wang, VP Georgiev, E Towie, SM Amoroso, ... IEEE Transactions on Electron Devices 62 (10), 3229-3236, 2015 | 26 | 2015 |
| Experimental and simulation study of silicon nanowire transistors using heavily doped channels VP Georgiev, MM Mirza, AI Dochioiu, F Adamu-Lema, SM Amoroso, ... IEEE Transactions on Nanotechnology 16 (5), 727-735, 2017 | 25 | 2017 |
| Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit T Al-Ameri, VP Georgiev, T Sadi, Y Wang, F Adamu-Lema, X Wang, ... Solid-State Electronics 129, 73-80, 2017 | 15 | 2017 |
| Impact of strain on the performance of Si nanowires transistors at the scaling limit: A 3D Monte Carlo/2D Poisson Schrodinger simulation study T Al-Ameri, VP Georgiev, FA Lema, T Sadi, X Wang, E Towie, C Riddet, ... 2016 International Conference on Simulation of Semiconductor Processes and …, 2016 | 15 | 2016 |
| Inverse Scaling Trends for Charge-Trapping-Induced Degradation of FinFETs Performance SM Amoroso, VP Georgiev, L Gerrer, E Towie, X Wang, C Riddet, ... Electron Devices, IEEE Transactions on 61 (12), 4014-4018, 2014 | 12 | 2014 |
| 3d multi-subband ensemble Monte Carlo simulator of FinFETs and nanowire transistors C Sampedro, L Donetti, F Gámiz, A Godoy, FJ Garcia-Ruiz, VP Georgiev, ... 2014 International Conference on Simulation of Semiconductor Processes and …, 2014 | 12 | 2014 |
| Design and analysis of the In0. 53Ga0. 47As implant-free quantum-well device structure B Benbakhti, K Kalna, KH Chan, E Towie, G Hellings, G Eneman, ... Microelectronic engineering 88 (4), 358-361, 2011 | 12 | 2011 |
| Variability-aware TCAD based design-technology co-optimization platform for 7nm node nanowire and beyond Y Wang, B Cheng, X Wang, E Towie, C Riddet, AR Brown, SM Amoroso, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 9 | 2016 |
| Predicting future technology performance A Asenov, C Alexander, C Riddet, E Towie Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013 | 9 | 2013 |
| Performance of vertically stacked horizontal Si nanowires transistors: A 3D Monte Carlo/2D Poisson Schrodinger simulation study T Al-Ameri, VP Georgiev, FA Lema, T Sadi, E Towie, C Riddet, ... 2016 IEEE Nanotechnology Materials and Devices Conference (NMDC), 1-2, 2016 | 8 | 2016 |
| One-dimensional multi-subband Monte Carlo simulation of charge transport in Si nanowire transistors T Sadi, E Towie, M Nedjalkov, C Riddet, C Alexander, L Wang, ... 2016 International Conference on Simulation of Semiconductor Processes and …, 2016 | 8 | 2016 |
| Monte Carlo analysis of In0.53Ga0.47as Implant-Free Quantum-Well device performance B Benbakhti, E Towie, K Kalna, G Hellings, G Eneman, K De Meyer, ... 2010 Silicon Nanoelectronics Workshop, 1-2, 2010 | 6 | 2010 |
| Numerical analysis of the new implant-free quantum-well CMOS: DualLogic approach B Benbakhti, KH Chan, E Towie, K Kalna, C Riddet, X Wang, G Eneman, ... Solid-state electronics 63 (1), 14-18, 2011 | 4 | 2011 |
| Experimental and simulation study of a high current 1D silicon nanowire transistor using heavily doped channels VP Georgiev, MM Mirza, AI Dochioiu, FA Lema, SM Amoroso, E Towie, ... 2016 IEEE Nanotechnology Materials and Devices Conference (NMDC), 1-3, 2016 | 3 | 2016 |
| Impact of the statistical variability on 15nm III–V and Ge MOSFET based SRAM design SY Liao, EA Towie, D Balaz, C Riddet, B Cheng, A Asenov 2013 14th International Conference on Ultimate Integration on Silicon (ULIS …, 2013 | 3 | 2013 |
| Remotely screened electron-impurity scattering model for nanoscale MOSFETs EA Towie, JR Watling, JR Barker Semiconductor science and technology 26 (5), 055008, 2011 | 3 | 2011 |
| Comparison of Si< 100> and< 110> crystal orientation nanowire transistor reliability using Poisson–Schrödinger and classical simulations L Gerrer, V Georgiev, SM Amoroso, E Towie, A Asenov Microelectronics Reliability 55 (9-10), 1307-1312, 2015 | 2 | 2015 |
| Silicon-on-insulator (SOI) fin-on-oxide field effect transistors (FinFETs) B Cheng, A Brown, E Towie, N Daval, KK Bourdelle, BY Nguyen, ... Silicon-On-Insulator (SOI) Technology, 195-211, 2014 | 2 | 2014 |
| 3D Monte Carlo Simulation of III-V Implant-Free Quantum-Well and FinFET MOSFETs EA Towie, C Riddet, A Asenov 16th International Workshop on Computational Electronics, 2013, 2013 | 2 | 2013 |
a asenovThe University of GlasgowVerified email at glasgow.ac.uk
