Talib Al-Ameri
TitleCited byYear
Nanowire Transistor Solutions for 5nm and Beyond
A Asenov, Y Wang, B Cheng, X Wang, P Asenov, T Al-Ameri, VP Georgiev
IEEE International Symposium on Quality Electronic Design (ISQED 2016) USA, 2016
182016
Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of n-type Nanowire Transistors
Y Wang, T Al-Ameri, X Wang, VP Georgiev, E Towie, SM Amoroso, ...
Electron Devices, IEEE Transactions on 62 (10), 3229 - 3236, 2015
182015
Impact of strain on the performance of Si nanowires transistors at the scaling limit: A 3D Monte Carlo / 2D Poisson Schrodinger simulation study
T Al-Ameri, VP Georgiev, FA Lema, T Sadi, X Wang, E Towie, C Riddet, ...
IEEE SISPAD 2016, Germany, 213-216, 2016
92016
Simulation Study of Vertically Stacked Lateral Si Nanowires Transistors for 5 nm CMOS Applications
T Al-Ameri, VP Georgiev, F Adamu-Lema, A Asenov
IEEE Journal of the Electron Devices Society 5 (6), 466 - 472, 2017
72017
Impact of Quantum Confinement on Transport and the Electrostatic Driven Performance of Silicon Nanowire Transistors at the Scaling Limit
T Al-Ameri, V Georgiev, T Sadi1, Y Wang, F Adamu-Lema, X Wang, ...
Solid-State Electronics 129, 73-80, 2017
72017
Correlation between Gate Length, Geometry and Electrostatic Driven Performance in Ultra-Scaled Silicon Nanowire Transistors
T Al-Ameri, Y Wang, VP Georgiev, F Adamu-Lema, X Wang, A Asenov
IEEE Nanotechnology Materials and Devices Conference (NMDC2015), USA, 1 - 5, 2015
72015
Influence of quantum confinement effects and device electrostatic driven performance in ultra-scaled SixGe1-x nanowire transistors
T Al-Ameri, VP Georgiev, F Adamu-Lema, X Wang, A Asenov
IEEE, EUROSOI-ULIS, Vienna, Austria, 2016
42016
Comparison between Bulk and FDSOI POM flash cell: a multiscale simulation study
VP Georgiev, SM Amoroso, TM Ali, L VilÓ-Nadal, C Busche, L Cronin, ...
IEEE Transactions on Electron Devices 62 (2), 680-684, 2015
32015
A Proposed Improvement Model for MC-CDMA in Selective Fading Channel
SM Salih, TM Ali
Anbar Journal of Engineering Sciences 2 (1), 1-10, 2009
32009
Vertically Stacked Lateral Si80Ge20 Nanowires Transistors for 5 nm CMOS Applications
T Al-Ameri, A Asenov
2017 Joint International EUROSOI Workshop and International Conference oná…, 2017
22017
Does a nanowire transistor follow the golden ratio? A 2D Poisson-Schr÷dinger/3D Monte Carlo simulation study
T Al-Ameri, VP Georgiev, F Adamu-Lema, A Asenov
International Conference onSimulation of Semiconductor Processes and Devicesá…, 2017
22017
Performance of Vertically Stacked Horizontal Si Nanowires Transistors: A 3D Monte Carlo / 2D Poisson Schrodinger Simulation Study
T Al-Ameri, VP Georgiev, FA Lema, T Sadi, E Towie, C Riddet, ...
IEEE Nanotechnology Materials and Devices Conference, France, 2016
22016
Influence of quantum confinement effects over device performance in circular and elliptical silicon nanowire transistors
V Georgiev, T Al-Ameri, Y Wang, L Gerrer, SM Amoroso, A Asenov
Computational Electronics (IWCE), West Lafayette, IN, USA, 1 - 4, 2015
22015
Design and Analysis of a 2.4 GHz, Fifth- Order Chebyshev Microstrip LPF
TM Ali
Journal of Telecommunications 21 (2), 6-12, 2013
2*2013
Correlation between the Golden Ratio and Nanowire Transistor Performance
T Al-Ameri
Applied Sciences 8 (1), 54, 2018
12018
Modelling and simulation study of NMOS Si nanowire transistors
T Al-Ameri
University of Glasgow, 2018
2018
Modelling and Simulation of Advanced Semiconductor Devices
F Adamu-Lema, M Duan, S Berrada, J Lee, T Al-Ameri, V Georgiev, ...
ECS Transactions 80 (4), 33-42, 2017
2017
Position-Dependent Performance in 5 nm Vertically Stacked Lateral Si Nanowires Transistors
T Al-Ameri, VP Georgiev, F Adamu-Lema, A Asenov
International Workshop on Computational Nanotechnology IWCN, 116-118, 2017
2017
Variability-aware Simulations of 5 nm Vertically Stacked Lateral Si Nanowires Transistors
T Al-Ameri, VP Georgiev, F Adamu-Lema, A Asenov
International Workshop on Computational Nanotechnology IWCN 2017, 79-81, 2017
2017
Statistical Variability in 5 nm Vertically Stacked Lateral Si Nanowire Transistors
T Al-Ameri
2017
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