Norbert Wehn
TitleCited byYear
Reliable on-chip systems in the nano-era: Lessons learnt and future trends
J Henkel, L Bauer, N Dutt, P Gupta, S Nassif, M Shafique, M Tahoori, ...
Proceedings of the 50th Annual Design Automation Conference, 99, 2013
Turbo-decoding without SNR estimation
A Worm, P Hoeher, N Wehn
IEEE Communications Letters 4 (6), 193-195, 2000
A synthesizable IP core for DVB-S2 LDPC code decoding
F Kienle, T Brack, N Wehn
Design, Automation and Test in Europe, 100-105, 2005
A synthesizable IP core for WIMAX 802.16 e LDPC code decoding
T Brack, M Alles, F Kienle, N Wehn
2006 IEEE 17th international symposium on personal, indoor and mobile radio …, 2006
A 477mW NoC-based digital baseband for MIMO 4G SDR
F Clermidy, C Bernard, R Lemaire, J Martin, I Miro-Panades, Y Thonnart, ...
2010 IEEE International Solid-State Circuits Conference-(ISSCC), 278-279, 2010
Low complexity LDPC code decoders for next generation standards
T Brack, M Alles, T Lehnigk-Emden, F Kienle, N Wehn, NE L'Insalata, ...
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
Automating RT-level operand isolation to minimize power consumption in datapaths
M Munch, B Wurth, R Mehra, J Sproch, N Wehn
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2000
Network-on-chip-centric approach to interleaving in high throughput channel decoders
C Neeb, MJ Thul, N Wehn
2005 IEEE International Symposium on Circuits and Systems, 1766-1769, 2005
A 150Mbit/s 3GPP LTE turbo code decoder
M May, T Ilnseher, N Wehn, W Raab
Proceedings of the Conference on Design, Automation and Test in Europe, 1420 …, 2010
DRAMPower: Open-source DRAM power & energy estimation tool
K Chandrasekar, C Weis, Y Li, S Goossens, M Jung, O Naji, B Akesson, ...
URL: http://www. drampower. info 22, 2012
Design and architectures for dependable embedded systems
J Henkel, L Bauer, J Becker, O Bringmann, U Brinkschulte, S Chakraborty, ...
Proceedings of the seventh IEEE/ACM/IFIP international conference on …, 2011
FlexiChaP: A reconfigurable ASIP for convolutional, turbo, and LDPC code decoding
M Alles, T Vogt, N Wehn
2008 5th International symposium on turbo codes and related topics, 84-89, 2008
Low complexity stopping criterion for LDPC code decoders
F Kienle, N Wehn
2005 IEEE 61st Vehicular Technology Conference 1, 606-609, 2005
A scalable system architecture for high-throughput turbo-decoders
MJ Thul, F Gilbert, T Vogt, G Kreiselmaier, N Wehn
Journal of VLSI signal processing systems for signal, image and video …, 2005
Exploiting expendable process-margins in DRAMs for run-time performance optimization
K Chandrasekar, S Goossens, C Weis, M Koedam, B Akesson, N Wehn, ...
Proceedings of the conference on Design, Automation & Test in Europe, 173, 2014
Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ
M Sadri, C Weis, N Wehn, L Benini
Proceedings of the 10th FPGAworld Conference, 5, 2013
Embedded DRAM development: Technology, physical design, and application issues
D Keitel-Schulz, N Wehn
IEEE Design & Test of Computers 18 (3), 7-15, 2001
Optimized concurrent interleaving architecture for high-throughput turbo-decoding
MJ Thul, F Gilbert, N Wehn
9th International Conference on Electronics, Circuits and Systems 3, 1099-1102, 2002
Error correction in single-hop wireless sensor networks: a case study
D Schmidt, M Berning, N Wehn
Proceedings of the Conference on Design, Automation and Test in Europe, 1296 …, 2009
A reconfigurable ASIP for convolutional and turbo decoding in an SDR environment
T Vogt, N Wehn
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 (10 …, 2008
The system can't perform the operation now. Try again later.
Articles 1–20