Antonio Pullini
Antonio Pullini
Verified email at iis.ee.ethz.ch
TitleCited byYear
Design issues and considerations for low-cost 3-D TSV IC technology
G Van der Plas, P Limaye, I Loi, A Mercha, H Oprins, C Torregiani, S Thijs, ...
IEEE Journal of Solid-State Circuits 46 (1), 293-307, 2010
3292010
Network-on-chip design and synthesis outlook
D Atienza, F Angiolini, S Murali, A Pullini, L Benini, G De Micheli
Integration 41 (3), 340-359, 2008
1582008
Fault tolerance overhead in network-on-chip flow control schemes
A Pullini, F Angiolini, D Bertozzi, L Benini
2005 18th Symposium on Integrated Circuits and Systems Design, 224-229, 2005
1162005
Bringing NoCs to 65 nm
A Pullini, F Angiolini, S Murali, D Atienza, G De Micheli, L Benini
IEEE Micro 27 (5), 75-85, 2007
922007
Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices
M Gautschi, PD Schiavone, A Traber, I Loi, A Pullini, D Rossi, E Flamand, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (10 …, 2017
752017
NoC design and implementation in 65nm technology
A Pullini, F Angiolini, P Meloni, D Atienza, S Murali, L Raffo, G De Micheli, ...
Proceedings of the First International Symposium on Networks-on-Chip, 273-282, 2007
732007
An IoT endpoint system-on-chip for secure and energy-efficient near-sensor analytics
F Conti, R Schilling, PD Schiavone, A Pullini, D Rossi, FK Gürkaynak, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2481-2494, 2017
642017
Networks on chips: From research to products
G De Micheli, C Seiculescu, S Murali, L Benini, F Angiolini, A Pullini
Proceedings of the 47th Design Automation Conference, 300-305, 2010
542010
A 60 gops/w,− 1.8 v to 0.9 v body bias ulp cluster in 28 nm utbb fd-soi technology
D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Bartolini, ...
Solid-State Electronics 117, 170-184, 2016
502016
PULP: A ultra-low power parallel accelerator for energy-efficient and flexible embedded vision
F Conti, D Rossi, A Pullini, I Loi, L Benini
Journal of Signal Processing Systems 84 (3), 339-354, 2016
392016
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis
S Bobba, J Zhang, A Pullini, D Atienza, G De Micheli
Proceedings of the Conference on Design, Automation and Test in Europe, 616-621, 2009
392009
PULP: A parallel ultra low power platform for next generation IoT applications
D Rossi, F Conti, A Marongiu, A Pullini, I Loi, M Gautschi, G Tagliavini, ...
2015 IEEE Hot Chips 27 Symposium (HCS), 1-39, 2015
382015
Timing-driven row-based power gating
A Sathanur, A Pullini, L Benini, A Macii, E Macii, M Poncino
Proceedings of the 2007 international symposium on Low power electronics and …, 2007
332007
193 MOPS/mW@ 162 MOPS, 0.32 V to 1.15 V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing
D Rossi, A Pullini, I Loi, M Gautschi, FK Gurkaynak, A Teman, ...
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), 1-3, 2016
312016
Timing-error-tolerant network-on-chip design methodology
R Tamhankar, S Murali, S Stergiou, A Pullini, F Angiolini, L Benini, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007
282007
Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores
M Gautschi, A Traber, A Pullini, L Benini, M Scandale, A Di Federico, ...
2015 IFIP/IEEE International Conference on Very Large Scale Integration …, 2015
272015
Energy-efficient vision on the PULP platform for ultra-low power parallel computing
F Conti, D Rossi, A Pullini, I Loi, L Benini
2014 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2014
272014
PULPino: A small single-core RISC-V SoC
A Traber, F Zaruba, S Stucki, A Pullini, G Haugou, E Flamand, ...
3rd RISCV Workshop, 2016
262016
Exploring architectural heterogeneity in intelligent vision systems
N Chandramoorthy, G Tagliavini, K Irick, A Pullini, S Advani, S Al Habsi, ...
2015 IEEE 21st International Symposium on High Performance Computer …, 2015
232015
Physically clustered forward body biasing for variability compensation in nanometer CMOS design
A Sathanur, A Pullini, L Benini, G De Micheli, E Macii
Proceedings of the Conference on Design, Automation and Test in Europe, 154-159, 2009
232009
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