Flavio M de Paula
Flavio M de Paula
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Cited by
Backspace: Formal analysis for post-silicon debug
FM De Paula, M Gort, AJ Hu, SJE Wilton, J Yang
2008 Formal Methods in Computer-Aided Design, 1-10, 2008
Industrial strength distributed explicit state model checking
B Bingham, J Bingham, FM De Paula, J Erickson, G Singh, M Reitblatt
2010 Ninth International Workshop on Parallel and Distributed Methods in …, 2010
An effective guidance strategy for abstraction-guided simulation
FM De Paula, AJ Hu
Proceedings of the 44th annual Design Automation Conference, 63-68, 2007
TAB-BackSpace: Unlimited-length trace buffers with zero additional on-chip overhead
FM De Paula, A Nahir, Z Nevo, A Orni, AJ Hu
Proceedings of the 48th Design Automation Conference, 411-416, 2011
The Chip is Ready. Am I done? On-chip Verification using Assertion Processors.
JAM Nacif, FM de Paula, H Foster, CJN Coelho Jr, AO Fernandes
VLSI-SOC, 111-, 2003
An assertion library for on-chip white-box verification at run-time
JA Nacif, FM de Paula, H Foster, C Coelho, FC Sica, DC da Silva, ...
Proceedings of Latin American Test WorkShop, 2003
nuTAB-BackSpace: Rewriting to normalize non-determinism in post-silicon debug traces
FM De Paula, AJ Hu, A Nahir
International Conference on Computer Aided Verification, 513-531, 2012
Formal-analysis-based trace computation for post-silicon debug
M Gort, FM De Paula, JJW Kuan, TM Aamodt, AJ Hu, SJE Wilton, J Yang
IEEE transactions on very large scale integration (VLSI) systems 20 (11 …, 2011
Application level hardware tracing for scaling post-silicon debug
D Pal, A Sharma, S Ray, FM De Paula, S Vasudevan
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
BackSpace: Moving towards reality
FM De Paula, M Gort, AJ Hu, SJE Wilton
2008 Ninth International Workshop on Microprocessor Test and Verification, 49-54, 2008
Lazy suspect-set computation: Fault diagnosis for deep electrical bugs
D Sengupta, FM de Paula, AJ Hu, A Veneris, A Ivanov
Proceedings of the great lakes symposium on VLSI, 189-194, 2012
EverLost: A Flexible Platform for Industrial-Strength Abstraction-Guided Simulation: (Tool Paper)
FM de Paula, AJ Hu
Computer Aided Verification: 18th International Conference, CAV 2006 …, 2006
An efficient rewriting framework for trace coverage of symmetric systems
FM De Paula, A Haran, B Bingham
NASA Formal Methods: 10th International Symposium, NFM 2018, Newport News …, 2018
PREACH: A distributed explicit state model checker
FM De Paula, B Bingham, J Bingham, J Erickson, M Reitblatt, G Singh
Technical Report TR-2010-05, University of British Columbia, 2010
Refactoring digital hardware designs with assertion libraries
FM De Paula, CN Coelho, H Foster, JA Nacif, J Tompkins, AO Fernandes, ...
Eighth IEEE International High-Level Design Validation and Test Workshop, 37-42, 2003
Trace-based generation of states within a system
FM De Paula, BD Bingham, A Haran
US Patent 11,481,534, 2022
Message selection for hardware tracing in system-on-chip post-silicon debugging
FM De Paula, D Pal, S Vasudevan, A Sharma
US Patent App. 16/448,091, 2020
Rewriting toward trace coverage analysis of symmetric systems
FM De Paula, A Haran, B Bingham
Innovations in Systems and Software Engineering 15 (3), 191-206, 2019
On-Chip Property Verification Using Assertion Processors
JAM Nacif, CN Coelho, H Foster, FM de Paula, E Mota, MRF Mota, ...
VLSI-SOC: From Systems to Chips: IFIP TC 10/WG 10.5 Twelfth International …, 2006
BackSpace: Formal Analysis for Post-Silicon Debug
AJ Hu, F De Paula, M Gort
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