| Roadmap on emerging hardware and technology for machine learning K Berggren, Q Xia, KK Likharev, DB Strukov, H Jiang, T Mikolajick, ... Nanotechnology 32 (1), 012002, 2020 | 174 | 2020 |
| Race logic: A hardware acceleration for dynamic programming algorithms A Madhavan, T Sherwood, D Strukov ACM SIGARCH Computer Architecture News 42 (3), 517-528, 2014 | 115 | 2014 |
| A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit B Chakrabarti, MA Lastras-Montaño, G Adam, M Prezioso, B Hoskins, ... Scientific reports 7 (1), 42429, 2017 | 111 | 2017 |
| Energy-efficient stochastic computing with superparamagnetic tunnel junctions MW Daniels, A Madhavan, P Talatchian, A Mizrahi, MD Stiles Physical review applied 13 (3), 034016, 2020 | 74 | 2020 |
| A computational temporal logic for superconducting accelerators G Tzimpragos, D Vasudevan, N Tsiskaridze, G Michelogiannakis, ... Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | 41 | 2020 |
| High-throughput pattern matching with CMOL FPGA circuits: Case for logic-in-memory computing A Madhavan, T Sherwood, DB Strukov IEEE transactions on very large scale integration (VLSI) systems 26 (12 …, 2018 | 27 | 2018 |
| Boosted race trees for low energy classification G Tzimpragos, A Madhavan, D Vasudevan, D Strukov, T Sherwood Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019 | 26 | 2019 |
| A 4-mm2 180-nm-CMOS 15-Giga-cell-updates-per-second DNA sequence alignment engine based on asynchronous race conditions A Madhavan, T Sherwood, D Strukov 2017 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2017 | 22 | 2017 |
| Vertical integration of memristors onto foundry CMOS dies using wafer-scale integration J Rofeh, A Sodhi, M Payvand, MA Lastras-Montaño, A Ghofrani, ... 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), 957-962, 2015 | 22 | 2015 |
| Temporal memory with magnetic racetracks H Vakili, MN Sakib, S Ganguly, M Stan, MW Daniels, A Madhavan, ... IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 6 …, 2020 | 19 | 2020 |
| A configurable CMOS memory platform for 3D-integrated memristors M Payvand, A Madhavan, MA Lastras-Montaño, A Ghofrani, J Rofeh, ... 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1378-1381, 2015 | 19 | 2015 |
| Temporal computing with superconductors G Tzimpragos, J Volk, D Vasudevan, N Tsiskaridze, G Michelogiannakis, ... IEEE Micro 41 (3), 71-79, 2021 | 16 | 2021 |
| Streaming batch eigenupdates for hardware neural networks BD Hoskins, MW Daniels, S Huang, A Madhavan, GC Adam, N Zhitenev, ... Frontiers in neuroscience 13, 793, 2019 | 16 | 2019 |
| Mutual control of stochastic switching for two electrically coupled superparamagnetic tunnel junctions P Talatchian, MW Daniels, A Madhavan, MR Pufall, E Jué, WH Rippard, ... Physical Review B 104 (5), 054427, 2021 | 15 | 2021 |
| Race logic: abusing hardware race conditions to perform useful computation A Madhavan, T Sherwood, D Strukov IEEE Micro 35 (3), 48-57, 2015 | 14 | 2015 |
| 3d reram arrays and crossbars: Fabrication, characterization and applications GC Adam, B Chrakrabarti, H Nili, B Hoskins, MA Lastras-Montaño, ... 2017 IEEE 17th International Conference on Nanotechnology (IEEE-Nano), 844-849, 2017 | 12 | 2017 |
| Implementation of a binary neural network on a passive array of magnetic tunnel junctions JM Goodwill, N Prasad, BD Hoskins, MW Daniels, A Madhavan, L Wan, ... Physical Review Applied 18 (1), 014039, 2022 | 8 | 2022 |
| Storing and retrieving wavefronts with resistive temporal memory A Madhavan, MD Stiles IEEE International Symposium on Circuits and Systems (ISCAS), 2019 | 8 | 2019 |
| Associative memories using complex-valued Hopfield networks based on spin-torque oscillator arrays N Prasad, P Mukim, A Madhavan, MD Stiles Neuromorphic Computing and Engineering 2 (3), 034003, 2022 | 7 | 2022 |
| Energy efficient computation with asynchronous races A Madhavan, T Sherwood, D Strukov Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 7 | 2016 |
Mark StilesFellow, National Institute of Standards and TechnologyVerified email at nist.gov
