Saugata Ghose
Citata da
Citata da
Google workloads for consumer devices: Mitigating data movement bottlenecks
A Boroumand, S Ghose, Y Kim, R Ausavarungnirun, E Shiu, R Thakur, ...
Proceedings of the Twenty-Third International Conference on Architectural …, 2018
Error characterization, mitigation, and recovery in flash-memory-based solid-state drives
Y Cai, S Ghose, EF Haratsch, Y Luo, O Mutlu
Proceedings of the IEEE 105 (9), 1666-1704, 2017
Processing data where it makes sense: Enabling in-memory computation
O Mutlu, S Ghose, J Gómez-Luna, R Ausavarungnirun
Microprocessors and Microsystems 67, 28-41, 2019
Low-cost inter-linked subarrays (LISA): Enabling fast inter-subarray data movement in DRAM
KK Chang, PJ Nair, D Lee, S Ghose, MK Qureshi, O Mutlu
2016 IEEE International Symposium on High Performance Computer Architecture …, 2016
Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation
K Hsieh, S Khan, N Vijaykumar, KK Chang, A Boroumand, S Ghose, ...
2016 IEEE 34th International Conference on Computer Design (ICCD), 25-32, 2016
Read disturb errors in MLC NAND flash memory: Characterization, mitigation, and recovery
Y Cai, Y Luo, S Ghose, O Mutlu
2015 45th Annual IEEE/IFIP International Conference on Dependable Systems …, 2015
Understanding latency variation in modern DRAM chips: Experimental characterization, analysis, and optimization
KK Chang, A Kashyap, H Hassan, S Ghose, K Hsieh, D Lee, T Li, ...
Proceedings of the 2016 ACM SIGMETRICS International Conference on …, 2016
Understanding reduced-voltage operation in modern DRAM devices: Experimental characterization, analysis, and mechanisms
KK Chang, AG Yağlıkçı, S Ghose, A Agrawal, N Chatterjee, A Kashyap, ...
Proceedings of the ACM on Measurement and Analysis of Computing Systems 1 (1 …, 2017
LazyPIM: An efficient cache coherence mechanism for processing-in-memory
A Boroumand, S Ghose, M Patel, H Hassan, B Lucia, K Hsieh, KT Malladi, ...
IEEE Computer Architecture Letters 16 (1), 46-50, 2016
Nanopore sequencing technology and tools for genome assembly: computational analysis of the current state, bottlenecks and future directions
D Senol Cali, JS Kim, S Ghose, C Alkan, O Mutlu
Briefings in bioinformatics 20 (4), 1542-1559, 2019
GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies
JS Kim, D Senol Cali, H Xin, D Lee, S Ghose, M Alser, H Hassan, O Ergin, ...
BMC genomics 19, 23-40, 2018
Simultaneous multi-layer access: Improving 3D-stacked memory bandwidth at low cost
D Lee, S Ghose, G Pekhimenko, S Khan, O Mutlu
ACM Transactions on Architecture and Code Optimization (TACO) 12 (4), 1-29, 2016
A modern primer on processing in memory
O Mutlu, S Ghose, J Gómez-Luna, R Ausavarungnirun
Emerging computing: from devices to systems: looking beyond Moore and Von …, 2022
Processing-in-memory: A workload-driven perspective
S Ghose, A Boroumand, JS Kim, J Gómez-Luna, O Mutlu
IBM Journal of Research and Development 63 (6), 3: 1-3: 19, 2019
MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices
A Tavakkol, J Gómez-Luna, M Sadrosadati, S Ghose, O Mutlu
16th USENIX Conference on File and Storage Technologies (FAST 18), 49-66, 2018
Vulnerabilities in MLC NAND flash memory programming: Experimental analysis, exploits, and mitigation techniques
Y Cai, S Ghose, Y Luo, K Mai, O Mutlu, EF Haratsch
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation
Y Luo, S Ghose, Y Cai, EF Haratsch, O Mutlu
Abstracts of the 2018 ACM International Conference on Measurement and …, 2018
Mosaic: a GPU memory manager with application-transparent support for multiple page sizes
R Ausavarungnirun, J Landgraf, V Miller, S Ghose, J Gandhi, ...
Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017
WARM: Improving NAND flash memory lifetime with write-hotness aware retention management
Y Luo, Y Cai, S Ghose, J Choi, O Mutlu
2015 31st Symposium on Mass Storage Systems and Technologies (MSST), 1-14, 2015
Design-induced latency variation in modern DRAM chips: Characterization, analysis, and latency reduction mechanisms
D Lee, S Khan, L Subramanian, S Ghose, R Ausavarungnirun, ...
Proceedings of the ACM on Measurement and Analysis of Computing Systems 1 (1 …, 2017
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