| Method of stacking thin substrates by transfer bonding R Nagarajan, CP Sankarapillai US Patent 7,326,629, 2008 | 212 | 2008 |
| Wafer-level package for micro-electro-mechanical systems R Nagarajan, CS Premachandran, Y Chen, V Kripesh US Patent 6,846,725, 2005 | 198 | 2005 |
| Advanced MEMS packaging John H Lau, Cheng Kuo Lee, C S Premachandran, Yu Aibin McGraw-Hill, 2010 | 180* | 2010 |
| A two axes scanning SOI MEMS micromirror for endoscopic bioimaging J Singh, JHS Teo, Y Xu, CS Premachandran, N Chen, R Kotlanka, ... Journal of Micromechanics and Microengineering 18 (2), 025001, 2007 | 119 | 2007 |
| Design and development of a 3D scanning MEMS OCT probe using a novel SiOB package assembly Y Xu, J Singh, CS Premachandran, A Khairyanto, KWS Chen, N Chen, ... Journal of Micromechanics and Microengineering 18 (12), 125005, 2008 | 70 | 2008 |
| Method of forming through-wafer interconnects for vertical wafer level packaging CP Sankarapillai, R Nagarajan, M Soundarapandian US Patent 7,183,176, 2007 | 56 | 2007 |
| Si-based microphone testing methodology and noise reduction CS Premachandran, Z Wang, TC Chai, SC Chong, MK Iyer Design, Test, Integration, and Packaging of MEMS/MOEMS 4019, 588-592, 2000 | 38 | 2000 |
| Development of novel intermetallic joints using thin film indium based solder by low temperature bonding technology for 3D IC stacking WK Choi, CS Premachandran, OS Chiew, X Ling, L Ebin, A Khairyanto, ... 2009 59th Electronic Components and Technology Conference, 333-338, 2009 | 33 | 2009 |
| A novel electrically conductive wafer through hole filled vias interconnect for 3D MEMS packaging CS Premachandran, R Nagarajan, C Yu, Z Xiolin, CS Choong 53rd Electronic Components and Technology Conference, 2003. Proceedings …, 2003 | 29 | 2003 |
| A novel, wafer-level stacking method for low-chip yield and non-uniform, chip-size wafers for MEMS and 3D SIP applications CS Premachandran, J Lau, L Xie, A Khairyanto, K Chen, MEP Pa, ... 2008 58th Electronic Components and Technology Conference, 314-318, 2008 | 28 | 2008 |
| A novel, wafer-level stacking method for low-chip yield and non-uniform, chip-size wafers for MEMS and 3D SIP applications CS Premachandran, J Lau, L Xie, A Khairyanto, K Chen, M Pa, M Chew, ... Electronic Components and Technology Conference, 314 - 318, 2008 | 28 | 2008 |
| Fabrication and testing of a wafer-level vacuum package for MEMS device CS Premachandran, SC Chong, S Liw, R Nagarajan IEEE Transactions on Advanced Packaging 32 (2), 486-490, 2009 | 27 | 2009 |
| A vertical wafer level packaging using through hole filled via interconnects by lift off polymer method for mems and 3d stacking applications CS Premachandran, RNS Mohanraj, CS Choong, MK Iyer Proceedings Electronic Components and Technology, 2005. ECTC'05., 1094-1098, 2005 | 23 | 2005 |
| Vacuum packaging development and testing for an uncooled IR bolometer device CS Premachandran, SC Chong, TC Chai, M Iyer 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE …, 2004 | 22 | 2004 |
| Microprobe for 3D bio-imaging, method for fabricating the same and use thereof CS Premachandran, J Singh, JS Paul, PV Ramana, CJR Sheppard US Patent 7,616,987, 2009 | 20 | 2009 |
| Design, fabrication, and assembly of an optical biosensor probe package for OCT (Optical Coherence Tomography) application CS Premachandran, A Khairyanto, KCW Sheng, J Singh, J Teo, ... IEEE transactions on advanced packaging 32 (2), 417-422, 2009 | 19 | 2009 |
| Design, Fabrication and Assembly of an Optical Biosensor Probe Package for OCT (Optical Coherence Tomography) Application CS Premachandran, KCW Sheng, J Singh, J Teo, X Yingshun, ... IEEE, 2007 | 19 | 2007 |
| Design and Development of Fine Pitch Copper/Low-K Wafer Level Package XZ Rao, V.S., HS Wee, R Rajoo, CS Premachandran, V Kripesh, ... Advanced Packaging, IEEE Transactions 33 (2), 377-388, 2010 | 18 | 2010 |
| C2W bonding method for MEMS applications CWS Kelvin, CS Premachandran, CW Kyoung, OSCX Ling, AKB Ratmin, ... 2008 10th Electronics Packaging Technology Conference, 1283-1287, 2008 | 18 | 2008 |
| Novel stress-free Keep Out Zone process development for via middle TSV in 20nm planar CMOS technology . Mohamed A Rabie ,C.S Premachandran, R Ranjan, MI Natarajan, ... Interconnect Technology Conference / Advanced Metallization Conference, 203-206, 2014 | 17* | 2014 |
Colin J. R. SheppardItalian Institute of TechnologyVerified email at iit.it
Colin J. R. SheppardItalian Institute of TechnologyVerified email at iit.it