A logic synthesis methodology for low-power ternary logic circuits S Kim, SY Lee, S Park, KR Kim, S Kang IEEE Transactions on Circuits and Systems I: Regular Papers 67 (9), 3138-3151, 2020 | 102 | 2020 |
Design of quad-edge-triggered sequential logic circuits for ternary logic S Kim, SY Lee, S Park, S Kang 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 37-42, 2019 | 13 | 2019 |
A fast and scalable qubit-mapping method for noisy intermediate-scale quantum computers S Park, D Kim, M Kweon, JY Sim, S Kang Proceedings of the 59th ACM/IEEE Design Automation Conference, 13-18, 2022 | 10 | 2022 |
Hybrid circuit mapping: leveraging the full spectrum of computational capabilities of neutral atom quantum computers L Schmid, S Park, S Kang, R Wille arXiv preprint arXiv:2311.14164, 2023 | 8 | 2023 |
ClusterNet: Routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural Networks K Min, S Kwon, SY Lee, D Kim, S Park, S Kang 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 1-9, 2023 | 3 | 2023 |
Mcqa: Multi-constraint qubit allocation for near-ftqc device S Park, D Kim, JY Sim, S Kang Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022 | 2 | 2022 |
Ternary logic circuit device S Kang, KIM Sunmean, LEE SungYun, P Sunghye US Patent App. 17/489,624, 2022 | 1 | 2022 |
Multi-Threshold Voltages Graphene Barristor-Based Ternary ALU S Park, S Kim, S Kang 2019 International SoC Design Conference (ISOCC), 25-26, 2019 | 1 | 2019 |
QNSA: Quantum Neural Simulated Annealing for Combinatorial Optimization S Kwon, D Kim, S Park, S Kim, S Kang 2024 25th International Symposium on Quality Electronic Design (ISQED), 1-7, 2024 | | 2024 |
Ternary logic circuit device S Kang, KIM Sunmean, P Sunghye, LEE SungYun US Patent App. 17/489,629, 2022 | | 2022 |
Apparatus for low power ternary logic circuit S Kang, P Sunghye, LEE SungYun, KIM Sunmean US Patent App. 17/175,570, 2022 | | 2022 |