Youngsoo Shin
Youngsoo Shin
Professor of Electrical Engineering, KAIST
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Cited by
Cited by
Power conscious fixed priority scheduling for hard real-time systems
Y Shin, K Choi
Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 134-139, 1999
Power optimization of real-time embedded systems on variable speed processors
Y Shin, K Choi, T Sakurai
IEEE/ACM International Conference on Computer Aided Design. ICCAD-2000. IEEE …, 2000
Architecting voltage islands in core-based system-on-a-chip designs
J Hu, Y Shin, N Dhanwada, R Marculescu
Proceedings of the 2004 international symposium on Low power electronics and …, 2004
Partial bus-invert coding for power optimization of application-specific systems
Y Shin, SI Chae, K Choi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (2), 377-383, 2001
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
Y Shin, J Seomun, KM Choi, T Sakurai
ACM Transactions on Design Automation of Electronic Systems (TODAES) 15 (4 …, 2010
Reliable memristive switching memory devices enabled by densely packed silver nanocone arrays as electric-field concentrators
BK You, JM Kim, DJ Joe, K Yang, Y Shin, YS Jung, KJ Lee
ACS nano 10 (10), 9478-9488, 2016
Partial bus-invert coding for power optimization of system level bus
Y Shin, SI Chae, K Choi
Proceedings of the 1998 international symposium on Low power electronics and …, 1998
Coupling-driven bus design for low-power application-specific systems
Y Shin, T Sakurai
Proceedings of the 38th annual Design Automation Conference, 750-753, 2001
Similar outcomes of locking compression plating and retrograde intramedullary nailing for periprosthetic supracondylar femoral fractures following total knee arthroplasty: a …
YS Shin, HJ Kim, DH Lee
Knee Surgery, Sports Traumatology, Arthroscopy 25, 2921-2928, 2017
Pin accessibility-driven cell layout redesign and placement optimization
J Seo, J Jung, S Kim, Y Shin
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
Early analysis tools for system-on-a-chip design
JA Darringer, RA Bergamaschi, S Bhattacharya, D Brand, A Herkersdorf, ...
IBM Journal of Research and Development 46 (6), 691-707, 2002
Power distribution analysis of VLSI interconnects using model order reduction
Y Shin, T Sakurai
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2002
Schedulability-driven performance analysis of multiple mode embedded real-time systems
Y Shin, D Kim, K Choi
Proceedings of the 37th Annual Design Automation Conference, 495-500, 2000
Pulsed-latch circuits: A new dimension in ASIC design
Y Shin, S Paik
IEEE Design & Test of Computers 28 (6), 50-57, 2011
Semicustom design methodology of power gated circuits for low leakage applications
HO Kim, Y Shin
IEEE Transactions on Circuits and Systems II: Express Briefs 54 (6), 512-516, 2007
Machine learning (ML)-guided OPC using basis functions of polar Fourier transform
S Choi, S Shim, Y Shin
Optical Microlithography XXIX 9780, 63-70, 2016
An integrated hardware-software cosimulation environment with automated interface generation
K Kim, Y Kim, Y Shin, K Choi
Proceedings Seventh IEEE International Workshop on Rapid System Prototyping …, 1996
Comparison of specific femoral short stems and conventional-length stems in primary cementless total hip arthroplasty
YS Shin, DH Suh, JH Park, JL Kim, SB Han
Orthopedics 39 (2), e311-e317, 2016
Power gating circuit and integrated circuit including same
HO Kim, J Choi, BH Lee, MJ Seo, Y Shin
US Patent 7,948,263, 2011
Narrow bus encoding for low-power DSP systems
Y Shin, K Choi, YH Chang
IEEE transactions on very large scale integration (VLSI) systems 9 (5), 656-660, 2001
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