| Rule extraction from trained ANN: A survey A Darbari TU Dresden, Germany, 2000 | 59 | 2000 |
| Hardware monitor to verify memory units A Darbari, I Singleton US Patent 10,580,511, 2020 | 54 | 2020 |
| Industrial-strength certified SAT solving through verified SAT proof checking A Darbari, B Fischer, J Marques-Silva Theoretical Aspects of Computing–ICTAC 2010: 7th International Colloquium …, 2010 | 37 | 2010 |
| A new approach for transient fault injection using symbolic simulation A Darbari, BA Hashimi, P Harrod, D Bradley On-Line Testing Symposium, 2008. IOLTS'08. 14th IEEE International, 93-98, 2008 | 30 | 2008 |
| Selective state retention design using symbolic simulation A Darbari, BM Al Hashimi, D Flynn, J Biggs 2009 Design, Automation & Test in Europe Conference & Exhibition, 1644-1649, 2009 | 17 | 2009 |
| Clock Verification A Darbari GB Patent GB2,519,181, 2015 | 13 | 2015 |
| Clock Verification A Darbari, IT Limited US Patent App. 14/674,555, 2015 | 13 | 2015 |
| Deadlock detection in hardware design using assertion based verification A Darbari, C McKellar US Patent 9,767,236, 2017 | 8 | 2017 |
| Assessing performance of a hardware design using formal evaluation logic A Darbari, I Singleton US Patent 10,331,831, 2019 | 7 | 2019 |
| Symmetry reduction for STE model checking using structured models A Darbari University of Oxford, 2006 | 7 | 2006 |
| Control path verification of hardware design for pipelined process A Darbari, S Elliott US Patent 10,325,044, 2019 | 6 | 2019 |
| Hardware Data Structure for Tracking Partially Ordered and Reordered transactions A Darbari GB Patent 2,530,208, 2016 | 6 | 2016 |
| Hardware Data Structure for Tracking Partially Ordered and Reordered Transactions A Darbari, IT LIMITED US Patent 20,160,062,931, 2016 | 6 | 2016 |
| Hardware Data Structure for Tracking Partially Ordered and Reordered transactions A Darbari GB Patent GB2,524,344, 2015 | 6 | 2015 |
| Livelock recovery circuit configured to detect illegal repetition of an instruction and transition to a known state A Darbari, I Singleton US Patent 10,552,155, 2020 | 5 | 2020 |
| Livelock detection in a hardware design using formal evaluation logic A Darbari, I Singleton US Patent 10,346,571, 2019 | 5 | 2019 |
| Hardware Data Structure for Tracking Ordered Transactions A Darbari GB Patent 2,529,971, 2016 | 5 | 2016 |
| Hardware Data Structure for Tracking Ordered Transactions A Darbari, IT LIMITED US Patent 20,160,062,941, 2016 | 5 | 2016 |
| Hardware Data Structure for Tracking Ordered Transactions A Darbari GB Patent GB2,524,128, 2015 | 5 | 2015 |
| Symmetry reduction for STE model checking A Darbari 2006 Formal Methods in Computer Aided Design, 97-105, 2006 | 5 | 2006 |
Bashir M. Al-HashimiProfessor of Computer Engineering, King’s College LondonVerified email at kcl.ac.uk
