Ashish Darbari
Ashish Darbari
FOUNDER & CEO, AXIOMISE
Verified email at DARBARI.ORG - Homepage
Title
Cited by
Cited by
Year
Personal computer integrated with personal digital assistant
S Du, B Denning, J Lam
US Patent 7,343,484, 2008
812008
Rule extraction from trained ANN: A survey
A Darbari
TU Dresden, Germany, 2000
562000
Industrial-strength certified SAT solving through verified SAT proof checking
A Darbari, B Fischer, J Marques-Silva
International Colloquium on Theoretical Aspects of Computing, 260-274, 2010
312010
A new approach for transient fault injection using symbolic simulation
A Darbari, BA Hashimi, P Harrod, D Bradley
On-Line Testing Symposium, 2008. IOLTS'08. 14th IEEE International, 93-98, 2008
242008
Selective state retention design using symbolic simulation
A Darbari, BM Al Hashimi, D Flynn, J Biggs
2009 Design, Automation & Test in Europe Conference & Exhibition, 1644-1649, 2009
122009
Clock Verification
A Darbari
GB Patent GB2,519,181, 2015
82015
Clock Verification
A Darbari, IT Limited
US Patent App. 14/674,555, 2015
82015
Symmetry reduction for STE model checking using structured models
A Darbari
University of Oxford, 2006
72006
Deadlock detection in hardware design using assertion based verification
A Darbari, C McKellar
US Patent 9,767,236, 2017
52017
Symmetry reduction for STE model checking
A Darbari
2006 Formal Methods in Computer Aided Design, 97-105, 2006
52006
Formalization and Execution of STE in HOL
A Darbari
Springer, 2003
42003
Industrial Strength Formal Using Abstractions
A Darbari, I Singleton
arXiv preprint arXiv:1606.02347, 2016
32016
Method and apparatus for distribution of digital signals on a wideband signal distribution system
E Hennenhoefer, R Snyder, R Stine
US Patent App. 10/346,571, 2003
32003
Formalization and execution of STE in HOL (extended version)
A Darbari
Oxford University, 2003
32003
Symbolic Trajectory Evaluation in a Nutshell
T Melham, A Darbari
Unpublished report, available on request, 2002
32002
Livelock detection in a hardware design using formal evaluation logic
A Darbari, I Singleton
US Patent 10,346,571, 2019
22019
Assessing performance of a hardware design using formal evaluation logic
A Darbari, I Singleton
US Patent 10,331,831, 2019
22019
Formalizing a SAT proof checker in Coq
A Darbari, B Fischer, J Marques-Silva
First Coq Workshop, published as technical report tum-i0919 of the Technical …, 2009
22009
Integrated IP network telephone distributor with switching and routing functions
CS Chang, W Chen
US Patent App. 10/067,896, 2003
22003
Control path verification of hardware design for pipelined process
A Darbari, S Elliott
US Patent App. 16/399,218, 2019
12019
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