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Dajiang Liu
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Polyhedral model based mapping optimization of loop nests for CGRAs
D Liu, S Yin, L Liu, S Wei
Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE, 1-8, 2013
782013
Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures
S Yin, X Yao, D Liu, L Liu, S Wei
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (5 …, 2016
512016
Data-Flow Graph Mapping Optimization for CGRA with Deep Reinforcement Learning
D Liu, S Yin, G Luo, J Shang, L Liu, S Wei, Y Feng, S Zhou
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018
472018
Improving nested loop pipelining on coarse-grained reconfigurable architectures
S Yin, D Liu, Y Peng, L Liu, S Wei
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (2), 507-520, 2016
252016
DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach
S Yin, D Liu, L Sun, L Liu, S Wei
Circuits and Systems (ISCAS), 2017 IEEE International Symposium on, 1-4, 2017
222017
Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory
S Yin, X Yao, T Lu, D Liu, J Gu, L Liu, S Wei
IEEE Transactions on Parallel and Distributed Systems, 2017
212017
Optimizing spatial mapping of nested loop for coarse-grained reconfigurable architectures
D Liu, S Yin, Y Peng, L Liu, S Wei
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (11 …, 2015
172015
Joint affine transformation and loop pipelining for mapping nested loop on CGRAs
S Yin, D Liu, L Liu, S Wei, Y Guo
Proceedings of the 2015 Design, Automation & Test in Europe Conference …, 2015
132015
Joint Modulo Scheduling and Assignment for Loop Mapping on Dual- CGRAs
S Yin, J Gu, D Liu, L Liu, S Wei
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016
122016
Towards High-Bandwidth-Utilization SpMV on FPGAs via Partial Vector Duplication
B Liu, D Liu
Proceedings of the 28th Asia and South Pacific Design Automation Conference …, 2023
82023
RF-CGRA: a routing-friendly CGRA with hierarchical register chains
R Zhu, B Wang, D Liu
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 262-267, 2022
72022
Towards High-Quality CGRA Mapping with Graph Neural Networks and Reinforcement Learning
Y Zhuang, Z Zhang, D Liu
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022
62022
Mapping optimization of affine loop nests for reconfigurable computing architecture
D Liu, S Yin, C Yin, L Liu, S Wei
IEICE TRANSACTIONS on Information and Systems 95 (12), 2898-2907, 2012
52012
Towards energy-efficient CGRAs via stochastic computing
B Wang, R Zhu, J Shang, D Liu
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 202-207, 2022
42022
Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures
S Yin, D Liu, L Sun, X Lin, L Liu, S Wei
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
42017
Mapping multi-level loop nests onto cgras using polyhedral optimizations
D Liu, S Yin, L Liu, S Wei
IEICE Transactions on Fundamentals of Electronics, Communications and …, 2015
32015
Polyhedral-based Pipelining of Imperfectly-Nested Loop for CGRAs
D Liu, T Liu, X Mo, J Shang, S Yin
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021
22021
Affine transformations for communication and reconfiguration optimization of loops on CGRAs
D Liu, S Yin, L Liu, S Wei
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on, 2541-2544, 2013
22013
A portable environmental monitoring system based on WSN for off-the-shelf sensors
D Liu, S Yin, J Chen, H Gao, S Wei
Computational Problem-Solving (ICCP), 2011 International Conference on, 1-4, 2011
22011
DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs
D Liu, D Mou, R Zhu, Y Zhuang, J Shang, J Zhong, S Yin
2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023
12023
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