| Trading off area, yield and performance via hybrid redundancy in multi-core architectures Y Gao, Y Zhang, D Cheng, MA Breuer 2013 IEEE 31st VLSI Test Symposium (VTS), 1-6, 2013 | 14 | 2013 |
| Application debug in FPGAs in the presence of multiple asynchronous clocks G Tzimpragos, D Cheng, S Tapp, B Jayadev, A Majumdar 2016 International Conference on Field-Programmable Technology (FPT), 189-192, 2016 | 11 | 2016 |
| A new march test for process-variation induced delay faults in srams D Cheng, H Hsiung, B Liu, J Chen, J Zeng, R Govindan, SK Gupta 2013 22nd Asian Test Symposium, 115-122, 2013 | 10 | 2013 |
| Maximizing yield per area of highly parallel CMPs using hardware redundancy D Cheng, SK Gupta IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 9 | 2014 |
| A novel software-based defect-tolerance approach for application-specific embedded systems D Cheng, S Gupta 2011 IEEE 29th International Conference on Computer Design (ICCD), 443-444, 2011 | 8 | 2011 |
| A systematic methodology to improve yield per area of highly-parallel CMPs D Cheng, SK Gupta 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2012 | 7 | 2012 |
| Architecture for reliable scan-dump in the presence of multiple asynchronous clock domains in FPGA SOCs A Majumdar, B Jayadev, D Cheng, A Lin 2017 IEEE 26th Asian Test Symposium (ATS), 139-144, 2017 | 5 | 2017 |
| Optimal redundancy designs for CNFET-based circuits D Cheng, F Wang, F Gao, SK Gupta 2014 IEEE 23rd Asian Test Symposium, 25-32, 2014 | 5 | 2014 |
| PPB: Partially-working processors binning for maximizing wafer utilization D Cheng, SK Gupta 2015 IEEE 33rd VLSI Test Symposium (VTS), 1-6, 2015 | 4 | 2015 |
| Optimizing redundancy design for chip-multiprocessors for flexible utility functions D Cheng, SK Gupta 2014 International Test Conference, 1-8, 2014 | 4 | 2014 |
| Field profiling & monitoring of payload transistors in FPGAs D Cheng, A Majumdar, X Wang, N Chong 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System …, 2017 | 3 | 2017 |
| Towards systematic roadmaps for networked systems B Liu, H Hsiung, D Cheng, R Govindan, S Gupta Proceedings of the 11th ACM Workshop on Hot Topics in Networks, 91-96, 2012 | 2 | 2012 |
| Runtime measurement of process variations and supply voltage characteristics D Cheng, N Chong, A Majumdar, PC Yeh, CW Chang US Patent 11,585,854, 2023 | 1 | 2023 |
| Interplay of Failure Rate, Performance, and Test Cost in TCAM under Process Variations H Hsiung, D Cheng, B Liu, R Govindan, SK Gupta 2013 22nd Asian Test Symposium, 251-258, 2013 | 1 | 2013 |
| DFT-enabled within-die AC uniformity and performance monitor structure for advanced process N Chong, IR Chen, D Cheng, A Majumdar, PC Yeh, J Chang 2018 IEEE International Conference on Microelectronic Test Structures (ICMTS …, 2018 | | 2018 |
| Can Networked Systems Benefit from Tomorrow’s Fast, but Unreliable, Memories? B Liu, D Cheng, H Hsiung, R Govindan, S Gupta | | |
Ramesh GovindanProfessor of Computer Science, University of Southern CaliforniaVerified email at usc.edu
Ramesh GovindanProfessor of Computer Science, University of Southern CaliforniaVerified email at usc.edu