Alessandro De Gennaro
Alessandro De Gennaro
IC design engineer, Tiempo Secure
Verified email at ncl.ac.uk - Homepage
Title
Cited by
Cited by
Year
A heuristic algorithm for deriving compact models of processor instruction sets
A de Gennaro, P Stankaitis, A Mokhov
2015 15th International Conference on Application of Concurrency to System …, 2015
92015
Reconfigurable asynchronous pipelines: From formal models to silicon
D Sokolov, A de Gennaro, A Mokhov
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
62018
Process windows
A Mokhov, J Cortadella, A de Gennaro
2017 17th International Conference on Application of Concurrency to System …, 2017
42017
Language and hardware acceleration backend for graph processing
A Mokhov, A De Gennaro, G Tarawneh, J Wray, G Lukyanov, S Mileiko, ...
Languages, Design Methods, and Tools for Electronic System Design, 71-88, 2019
32019
Distributed event-based computing
A Brown, D Thomas, J Reeve, G Tarawneh, A De Gennaro, M Naylor, ...
IOS Press, 2018
32018
Language and hardware acceleration backend for graph processing
A Mokhov, A De Gennaro, G Tarawneh, J Wray, G Lukyanov, S Mileiko, ...
FDL 2017 Forum on Specification & Design Languages, Verona, Italy, IEEE., 2017
32017
Efficient composition of scenario-based hardware specifications
A de Gennaro, P Stankaitis, A Mokhov
IET Computers & Digital Techniques 13 (2), 57-69, 2018
12018
Design and Implementation of Reconfigurable Asynchronous Pipelines
A de Gennaro, D Sokolov, A Mokhov
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (6 …, 2020
2020
Hardware Synthesis from High-level Scenario Specifications
A de Gennaro
PhD thesis, Newcastle University, 2019
2019
Prototyping Resilient Processing Cores in Workcraft
G Lukyanov, A de Gennaro, A Mokhov, P Stankaitis, M Rykunov
2nd International Workshop on Resiliency in Embedded Electronic Systems, 2017
2017
Modelling concurrency in processor instruction sets
A de Gennaro
2015
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Articles 1–11