Mehdi Modarressi
Mehdi Modarressi
Assistant Prof. of Computer Engineering, School of ECE, University of Tehran
Verified email at - Homepage
Cited by
Cited by
Application-aware topology reconfiguration for on-chip networks
M Modarressi, A Tavakkol, H Sarbazi-Azad
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (11), 2010
Virtual point-to-point connections for NoCs
M Modarressi, A Tavakkol, H Sarbazi-Azad
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
A hybrid packet-circuit switched on-chip network based on SDM
M Modarressi, H Sarbazi-Azad, M Arjomand
2009 Design, Automation & Test in Europe Conference & Exhibition, 566-569, 2009
Power-aware mapping for reconfigurable NoC architectures
M Modarressi, H Sarbazi-Azad
2007 25th International Conference on Computer Design, 417-422, 2007
Fast data delivery for many-core processors
M Bakhshalipour, P Lotfi-Kamran, A Mazloumi, F Samandi, ...
IEEE Transactions on Computers 67 (10), 1416-1429, 2018
An energy-efficient virtual channel power-gating mechanism for on-chip networks
A Mirhosseini, M Sadrosadati, A Fakhrzadehgan, M Modarressi, ...
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
A reconfigurable fault-tolerant routing algorithm to optimize the network-on-chip performance and latency in presence of intermittent and permanent faults
RJ Behrouz, M Modarressi, HS Azad
2011 IEEE 29th International Conference on Computer Design (ICCD), 433-434, 2011
An efficient dynamically reconfigurable on-chip network architecture
M Modarressi, H Sarbazi-Azad, A Tavakkol
Design Automation Conference, 166-169, 2010
An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors
P Lotfi-Kamran, M Modarressi, H Sarbazi-Azad
IEEE Transactions on Computers, 0
Near-ideal networks-on-chip for servers
P Lotfi-Kamran, M Modarressi, H Sarbazi-Azad
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
Power-efficient accelerator design for neural networks using computation reuse
A Yasoubi, R Hojabr, M Modarressi
IEEE Computer Architecture Letters 16 (1), 72-75, 2016
Daylight adaptive smart indoor lighting control method using artificial neural networks
A Seyedolhosseini, N Masoumi, M Modarressi, N Karimian
Journal of Building Engineering 29, 101141, 2020
Reconfigurable network-on-chip for 3D neural network accelerators
A Firuzan, M Modarressi, M Daneshtalab, M Reshadi
2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2018
A reconfigurable cache architecture for object-oriented embedded systems
M Modarressi, S Hessabi, M Goudarzi
2006 Canadian Conference on Electrical and Computer Engineering, 959-962, 2006
Customizing clos network-on-chip for neural networks
R Hojabr, M Modarressi, M Daneshtalab, A Yasoubi, A Khonsari
IEEE Transactions on Computers 66 (11), 1865-1877, 2017
Reconfigurable communication fabric for efficient implementation of neural networks
A Firuzan, M Modarressi, M Daneshtalab
2015 10th International Symposium on Reconfigurable Communication-centric …, 2015
Dynamic Resource Sharing for High-Performance 3-D Networks-on-Chip
S Rezaei, S Hossein, A Mazloumi, M Modarressi, P Lotfi-Kamran
IEEE Computer Architecture Letters, 0
Power and performance efficient partial circuits in packet-switched networks-on-chip
N Teimouri, M Modarressi, H Sarbazi-Azad
2013 21st Euromicro International Conference on Parallel, Distributed, and …, 2013
Using task migration to improve non-contiguous processor allocation in NoC-based CMPs
M Modarressi, M Asadinia, H Sarbazi-Azad
Journal of Systems Architecture 59 (7), 468-481, 2013
Nom: Network-on-memory for inter-bank data transfer in highly-banked memories
SHSA Rezaei, M Modarressi, R Ausavarungnirun, M Sadrosadati, O Mutlu, ...
IEEE Computer Architecture Letters 19 (1), 80-83, 2020
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