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Rakesh Kumar
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Blasting through the Front-End Bottleneck with Shotgun
R Kumar, B Grot, V Nagarajan
Proceedings of the Twenty-Third International Conference on Architectural …, 2018
622018
Boomerang: A Metadata-Free Architecture for Control Flow Delivery
R Kumar, CC Huang, B Grot, V Nagarajan
High Performance Computer Architecture (HPCA), 2017 IEEE International …, 2017
612017
C 3 D: Mitigating the NUMA bottleneck via coherent DRAM caches
CC Huang, R Kumar, M Elver, B Grot, V Nagarajan
Microarchitecture (MICRO), 2016 49th Annual IEEE/ACM International Symposium …, 2016
252016
Twig: Profile-Guided BTB Prefetching for Data Center Applications
TA Khan, N Brown, A Sriraman, N Soundararajan, R Kumar, J Devietti, ...
54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2021
232021
Freeway: Maximizing MLP for Slice-Out-of-Order Execution
R Kumar, M Alipour, D Black-Schaffer
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
232019
Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment
R Kumar, A Martínez, A González
ACM Transactions on Architecture and Code Optimization (TACO) 11 (3), 25, 2014
202014
Dynamic selective devectorization for efficient power gating of SIMD units in a HW/SW co-designed environment
R Kumar, A Martínez, A González
Computer Architecture and High Performance Computing (SBAC-PAD), 2013 25th …, 2013
202013
DARCO: Infrastructure for Research on HW/SW co-designed Virtual Machines
D Pavlou, A Brankovic, R Kumar, M Gregori, K Stavrou, E Gibert, ...
Proceedings of the 4th Workshop on Architectural and Microarchitectural …, 2011
172011
Delay and bypass: Ready and criticality aware instruction scheduling in out-of-order processors
M Alipour, S Kaxiras, D Black-Schaffer, R Kumar
2020 IEEE International Symposium on High Performance Computer Architecture …, 2020
162020
FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors
M Alipour, R Kumar, S Kaxiras, D Black-Schaffer
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 716-721, 2019
13*2019
Speculative dynamic vectorization for HW/SW co-designed processors
R Kumar, A Martínez, A González
Proceedings of the 21st international conference on Parallel architectures …, 2012
132012
Branch target buffer for a data processing apparatus
R Kumar, B Grot, V Nagarajan, CC Huang
112018
BTB-X: A Storage-Effective BTB Organization
T Asheim, B Grot, R Kumar
IEEE Computer Architecture Letters, 2021
102021
Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned Environment
R Kumar, A Martínez, A González
ACM Transactions on Computer Systems (TOCS) 33 (4), 12, 2016
82016
Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment
R Kumar, A Martínez, A González
High Performance Computing (HiPC), 2013 20th International Conference on, 79-88, 2013
82013
Vectorizing for wider vector units in a HW/SW co-designed environment
R Kumar, A Martínez, A González
High Performance Computing and Communications & 2013 IEEE International …, 2013
82013
A Storage-Effective BTB Organization for Servers
T Asheim, B Grot, R Kumar
2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023
52023
Uncovering Hidden Instructions in Armv8-A Implementations
F Strupe, R Kumar
Workshop on Hardware and Architectural Support for Security and Privacy, 2020
52020
Shooting Down the Server Front-End Bottleneck
R Kumar, B Grot
ACM Transactions on Computer Systems (TOCS) 38 (3-4), 1-30, 2022
42022
A specialized btb organization for servers
T Asheim, B Grot, R Kumar
Proceedings of the 31st International Conference on Parallel Architectures …, 2022
42022
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